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sometimes called CML |
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== Explanation ==
[[Transistor-transistor logic|TTL]] and related families use transistors as [[digital]] [[switch]]es where transistors are either cut off or [[saturated]], depending on the state of the circuit.
ECL gates use [[differential amplifier]] configurations at the input stage. A [[bias]] configuration supplies a constant [[voltage]] at the midrange of the low and high logic levels to the [[differential amplifier]], so that the appropriate logical function of the input voltages will control the amplifier and the base of the output transistor (this output transistor is used in [[common collector]] configuration). The propagation time for this arrangement can be less than a nanosecond, making it the fastest logic family through several years.
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